1. Field of the Invention
The present invention generally relates to nonvolatile semiconductor memory devices, and particularly relates to a programming circuit and programming method for use in a nonvolatile semiconductor memory device.
2. Description of the Related Art
In general, nonvolatile semiconductor memory devices such as flash memories use a current flowing through a reference cell having a predetermined threshold as a reference current, and compare a drain current of a memory cell read at the time of read operation with the reference current. Determination as to whether the data is “1” or “0” varies depending on whether the drain current of the read memory cell is greater than the reference current.
As the number of rewrite operations with respect to a flash memory increases, charge loss by which written charge is lost begins to occur, creating a tendency that the threshold of the memory cells in the core circuit decreases. With respect to those reference cells for which rewrite operations are not performed generally, on the other hand, the threshold stays fixed. As the number of rewrite operations increases, thus, there will be a situation in which the fixed threshold of a reference cell cannot provide a sufficient read margin.
As a method for obviating this problem, there is a dynamic reference read method. In this method, two types of reference cells corresponding to data “1” and data “0” are prepared as read reference cells, and the average is used as a reference current. In addition, these reference cells are subjected to rewrite operations in the same manner as memory cells. Namely, a reference cell Ref0 corresponding to programmed data “0” and a reference cell Ref1 corresponding to erased data “1” are provided, and an average of the two reference currents is used as a read reference current. Also, program/erase operations are performed on the reference cells concurrently with program/erase operations performed on the memory cells of the core circuit, thereby creating charge loss in the reference cells in the same manner as creating charge loss in the memory cells. This makes it possible to secure a sufficient read margin.
In the dynamic reference read method, a given reference cell is shared by a plurality of memory cells. When a given memory cells is programmed, a corresponding reference cell is also programmed. In this case, other memory cells sharing this reference cell suffers from an insufficient read margin when charge loss occurs. In order to avoid this, the other memory cells sharing this reference cell must be refreshed so as to be kept to the same level as the programmed memory cell.
FIG. 1 is a flowchart showing an algorithm of a related-art program operation. FIG. 1 shows a flowchart of a page program method that programs data for a plurality of words by use of a page buffer.
At step ST1, program data is input into data latches of the page buffer. Here, one page is comprised of 16 words, for example. Two words among these 16 words, for example, receive the program data (write data).
At step ST2, pre-read operation is performed to read data from the memory cell array of the core circuit corresponding to the addresses in the page subjected to the program operation. The read data is stored in the data latches to which the program data was not input at step ST1. With this provision, those words which are not subjected to the program operation undergo a refresh operation (rewrite operation).
At step ST3, a program verify operation is performed. At step ST4, a check is made based on the result of the program verify operation as to whether the verify operation produces a pass result. If it fails, at step ST5, a program operation is performed with respect to the relevant memory cells (including program operations for the memory cells to be refreshed). The procedure then returns to step ST3, followed by performing the operations described above. If all the bits pass the verify operation, the procedure comes to an end.
A certain-type flash memory can store 2-bit information in a single memory cell by storing electric charge in a trap layer comprised of a nitride film or the like. In this kind of flash memory, a film comprised of an oxide film, a nitride film, and an oxide film is formed between the control gate and the substrate, and the nitride film traps electric charge therein to change the threshold, which represents data “0” or data “1”. In this case, the trap layer comprised of the nitride film or the like is an insulating film, so that the electric charge does not move. The opposite ends of the trap layer can then store electric charge separately from each other, thereby storing 2-bit information in a single cell. Each bit of the 2-bit information can be independently retrieved by exchanging the roles between the drain and the source at the time of read operation.
Writing to the memory cell is performed through the injection of electron by channel hot electron. 9 V is applied to the gate electrode, 5 V applied to the drain, and 0 V applied to the source and the substrate, for example, thereby trapping hot electron generated in the channel. At this time, the hot electron is injected into the nitride film on the side near the drain. An erase operation is performed through the injection of hole by hot hole injection. Namely, −6 V is applied to the gate electrode, and 6 V applied to the drain, thereby injecting, into the nitride film, hole generated by an inter-band tunnel current running from the drain to the substrate. This neutralizes and erases the electric charge. When electric charge amounting to 2 bits is stored in one cell, the same voltage as applied to the drain is applied to the source to perform an erase operation. A read operation is carried out through a reverse read, which reverses the position of the drain from the drain position used in the write operation. Namely, a diffusion layer situated opposite the diffusion layer to which approximately 5 V is applied at the time of write operation is used as a drain, with 5V applied to the gate electrode, 1.5 V applied to the drain, and 0 V applied to the source and the substrate. If electric charge is stored in the nitride film on the side near the source, the trapped electric charge prevents the creation of a channel, resulting in no flow of an electric current. This makes it possible to read data “0”.
In the flash memory that can store 2 bits in one cell as described above, the threshold relating to the reading of one of the two bits changes in response to the state of the bit that is opposite the bit selected for the read operation. That is, if the opposite bit from the one selected for the read operation is in the programmed state, the threshold is relatively large due to the effect of trapped electric charge that is programmed. If the opposite bit from the one selected for the read operation is in the erased state, the threshold is relatively small due to the absence of trapped electric charge corresponding to the erased state.
The dynamic reference read method described above may create an over-programmed state through refresh operations if the charge loss of the refreshed memory cells is small. Namely, it is possible to result in the state in which electric charge is overly injected. In this case, the flash memory capable of storing 2 bits encounters a problem in that the threshold may exhibit a rise that is not negligible at the opposite bit from the bit that is overly programmed.
[Patent Document 1] Japanese Patent Application Publication No. 2001-76496.